FIG. 1 (Prior Art) is a simplified top-down diagram illustrative of a field programmable gate array (FPGA) integrated circuit 1. Integrated circuit 1 includes a ring of bond pads 2, an inner core of configurable logic blocks 3, and a fork-shaped clock distribution network 4. A clock signal present on a clock input bonding pad 5 passes through a clock buffer 6, is distributed vertically through a vertical clock bus 7, passes through clock buffers 8-12, and then propagates horizontally from left to right through corresponding horizontally extending clock buses 13-17. In the bottom most clock bus 17, the clock signal propagates left to right from node N at the output of clock buffer 12 and down the clock bus to node N8. The difference in time between the time when the clock signal arrives at node N and the time when the clock signal arrives at node N8 is called "clock skew". It is often desired to reduce this clock skew. One way to decrease clock skew is to increase clock signal propagation speed.
The theoretical maximum propagation speed v of a signal down a conductor in an integrated circuit is approximated in accordance with equation 1 below. ##EQU1##
The constant c in equation 1 is the speed of light in free space (3.times.10.sup.8 meters per second). The constant K is the dielectric constant of the dielectric material separating the conductor from other conductors in the integrated circuit.
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of a portion of integrated circuit 1 showing a section of clock bus 17. Numerous layers of metalization 20 and dielectric material 21 are disposed over the substrate 22 of the integrated circuit 1. In the illustrated example, the metal of the clock bus 17 is insulated from other layers of metal above it and below it by dielectric material 21. In a conventional integrated circuit, dielectric material 21 is silicon dioxide. Silicon dioxide has a dielectric constant of approximately four. Substituting the number four for the constant K in equation 1 indicates that a clock signal should theoretically be able to propagate down a clock bus at about 1.5.times.10.sup.8 meters per second (half the speed of light in free space).
Actual clock signals are, however, observed to travel at slower speeds. A real clock bus that extends across an integrated circuit has a significant distributed series resistance. This series resistance serves to limit the maximum propagation speed of the clock signal to a value below that of the theoretical 1.5.times.10.sup.8 meters per second limit.
FIG. 3 (Prior Art) illustrates a string of RC trees 23 that is often used to model the propagation of a clock signal down a buffered clock bus in an integrated circuit. Nodes N and N8 in FIG. 3 correspond to nodes N and N8, respectively, in FIG. 1. For the signal to propagate from node N to node N1, a current I must flow from node N through a series resistance R to charge the capacitor on node N1. The rate of increase of the voltage signal at node N1 is therefore limited by the series resistance R between nodes N and N1. When the voltage on node N1 increases, a current I1 can flow through the next series resistance R to charge the next capacitor on node N2. Such charging currents ripple down the string of RC trees of the structure of FIG. 3. It is therefore seen that the propagation speed of the signal is limited by resistance R and capacitance C. Because currents have to flow over these series resistances R to charge the capacitors C, larger values of R and C decrease the propagation speed of the signal. These series resistances R have the effect of limiting signal propagation speed to a value below the theoretical maximum as well as attenuating the signal. Consistent with the model of FIG. 3, clock signal propagation speed in an exemplary type of conventional field programmable gate array (FPGA) is about 2.times.10.sup.6 meters per second.
For very high frequency clock signals, preserving the signal requires periodic buffering, and is illustrated in FIG. 3 by the pairs of inverters following each illustrated resistor R. In an effort to increase clock signal propagation speeds, conventional clock buses are often realized as wide traces of metal in order to decrease series resistance. Although increasing trace width serves to decrease series resistance, it also serves to increase distributed capacitance which again limits clock signal propagation speed. A solution to this quandary is desired.
Not only do increased resistance and capacitance limit propagation speed, but they also increase power consumption. The power P consumed by the clock bus modeled in FIG. 3 may be approximated in accordance with equation 2 below. EQU P=CV.sup.2 f (equ.2)
The constant C in equation 2 is the total capacitance of the bus. The constant V in equation 2 is the voltage amplitude of the signal. The constant f in equation 2 is the frequency of the clock signal. In one example of a conventional integrated circuit, the metal trace of the clock bus is made about 1.5 microns wide in order to decrease series resistance. Buffering is required between each node, as shown in FIG. 3, in order to assure proper operation. Each 2500 micron long section of this clock bus between nodes has a 35 ohm series resistance R. The distributed capacitance C at each node is about 0.675 picofarads. Buffering adds power dissipation as well. In accordance with equation 2, approximately 15 milliwatts are required to propagate a 1.65 volt clock signal along the metal portion of the clock bus. Approximately 51 milliwatts are dissipated by the buffers. Thus propagating a signal down such a clock bus at one gigahertz requires approximately 66 milliwatts. This is an undesirably large amount of power.
Circuits and methods for increasing clock signal propagation speeds and/or for reducing the associated power consumption are sought.